1. Technical Field
The present disclosure relates to a semiconductor memory device, and more particularly, to a column decoder of a semiconductor memory device and a method of generating a column selection line signal in the semiconductor memory device.
2. Discussion of the Related Art
In general, a semiconductor memory device such as DRAM includes a memory cell array for storing data. A memory cell in the memory cell array is designated (or selected) by a row address and a column address so data can be read from the memory cell and written to the memory cell.
Semiconductor memory devices select the row address and the column address by decoding an address of a memory cell applied together with a write command or a read command. In general, a column selection line is used for selecting the column address. A column decoder used for activating the column selection line, includes a pre-decoder and a main decoder.
FIG. 1 is a timing diagram showing the operation of a column decoder of a semiconductor memory device according to the prior art.
A pre-decoded column address DCAi is a signal obtained by a pre-decoder of a semiconductor memory device by decoding an internal column address and used with a read operation and a write operation of the semiconductor memory device. The pre-decoded column address DCAi is synchronized with a rising edge of an external clock signal CLK.
The main decoder of the semiconductor memory device activates the column selection line signal (not shown) by combining logic states of the pre-decoded column address DCA<1> valid in the read operation and the read column enable signal R_CSLE activated to a high level. The column selection line signal activates the column selection line of the semiconductor memory device.
In addition, the main decoder of the semiconductor memory device activates the column selection line signal by combining logic states of the pre-decoded column address DCA<1> valid in the write operation and the write column enable signal W_CSLE activated to a high level.
In the read operation of the semiconductor memory device, the read column enable signal R_CSLE for enabling (or activating) the main decoder of the semiconductor memory device is activated to a high level in the time interval of the valid pre-decoded column address DCA<1>. The read column enable signal R_CSLE is activated to a high level in synchronization with (or in response to) the rising edge of the first cycle CLK1 of an external clock signal CLK applied from outside the semiconductor memory device, and deactivated to a low level in synchronization with the rising edge of the second cycle CLK2 of the external clock signal CLK.
The time interval from the rising edge of the first cycle CLK1 to the time when the read column enable signal R_CSLE is activated to a high level is an absolute timing margin ATM_R, and is a fixed time interval independent of the operating frequency of the semiconductor memory device, which is needed for the read operation.
In the write operation of the semiconductor memory device, the write column enable signal W_CSLE for activating the main decoder of the semiconductor memory device is activated to a high level in the time interval of the valid pre-decoded column address DCA<1>. The write column enable signal W_CSLE is activated to a high level in synchronization with the rising edge of the first cycle CLK1 of the external clock signal CLK, and is deactivated to a low level in synchronization with the rising edge of the second cycle CLK2 of the external clock signal CLK. The time interval during which the write column enable signal has the high level is the same as the time interval during which the read column enable signal has the high level.
The time interval from the rising edge of the first cycle CLK1 to the time when the write column enable signal W_CSLE is activated to a high level is an absolute timing margin ATM_W and is a fixed time interval independent of the operating frequency of the semiconductor memory device, which is needed for the write operation.
The read operation of the semiconductor memory device is quicker than the write operation, because the data read path of the read operation is shorter than the data write path of the write operation, so the absolute timing margin of the read operation ATM_R is shorter than the absolute timing margin of the write operation ATM_W.
The time interval from the time when the read column enable signal R_CSLE is deactivated to a low level to the rising edge of the third cycle CLK3 of the external clock signal CLK is a read frequency timing margin FTM_R, and is a variable time interval dependent on the operating frequency of the semiconductor memory device. The higher the operating frequency of the semiconductor memory device, the shorter the read frequency timing margin.
Similarly, the time interval from the time when the write column enable signal W_CSLE is deactivated to a low level to the rising edge of the third cycle CLK3 of the external clock signal CLK is a write frequency timing margin FTM_W, and is a variable time interval dependent on the operating frequency of the semiconductor memory device. The higher the operating frequency of the semiconductor memory device, the shorter the write frequency timing margin.
Since the absolute timing margin of the write operation ATM_W is longer than the absolute timing margin of the read operation ATM_R, the write frequency timing margin FTM_W is shorter than the read frequency timing margin FTM_R.
Accordingly, when the operating frequency of the semiconductor memory device is relatively high, for example 800 MHz, an invalid pre-decoded column address DCA<2> can be decoded in response to the write column enable signal W_CSLE at a high level. As a consequence, since an invalid column selection line signal is generated, the write operation of the semiconductor memory device may malfunction.